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<title>MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values </title></head>
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<h1>MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 10 /r</p>
<p>MOVUPS xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Move unaligned packed single-precision floating-point from xmm2/mem to xmm1.</td></tr>
<tr>
<td>
<p>0F 11 /r</p>
<p>MOVUPS xmm2/m128, xmm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>SSE</td>
<td>Move unaligned packed single-precision floating-point from xmm1 to xmm2/mem.</td></tr>
<tr>
<td>
<p>VEX.128.0F.WIG 10 /r</p>
<p>VMOVUPS xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move unaligned packed single-precision floating-point from xmm2/mem to xmm1.</td></tr>
<tr>
<td>
<p>VEX.128.0F 11.WIG /r</p>
<p>VMOVUPS xmm2/m128, xmm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move unaligned packed single-precision floating-point from xmm1 to xmm2/mem.</td></tr>
<tr>
<td>
<p>VEX.256.0F 10.WIG /r</p>
<p>VMOVUPS ymm1, ymm2/m256</p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move unaligned packed single-precision floating-point from ymm2/mem to ymm1.</td></tr>
<tr>
<td>
<p>VEX.256.0F 11.WIG /r</p>
<p>VMOVUPS ymm2/m256, ymm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move unaligned packed single-precision floating-point from ymm1 to ymm2/mem.</td></tr>
<tr>
<td>
<p>EVEX.128.0F.W0 10 /r</p>
<p>VMOVUPS xmm1 {k1}{z}, xmm2/m128</p></td>
<td>FVM-RM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Move unaligned packed single-precision floating-point values from xmm2/m128 to xmm1 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.0F.W0 10 /r</p>
<p>VMOVUPS ymm1 {k1}{z}, ymm2/m256</p></td>
<td>FVM-RM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Move unaligned packed single-precision floating-point values from ymm2/m256 to ymm1 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.0F.W0 10 /r</p>
<p>VMOVUPS zmm1 {k1}{z}, zmm2/m512</p></td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move unaligned packed single-precision floating-point values from zmm2/m512 to zmm1 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.128.0F.W0 11 /r</p>
<p>VMOVUPS xmm2/m128 {k1}{z}, xmm1</p></td>
<td>FVM-MR</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Move unaligned packed single-precision floating-point values from xmm1 to xmm2/m128 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.0F.W0 11 /r</p>
<p>VMOVUPS ymm2/m256 {k1}{z}, ymm1</p></td>
<td>FVM-MR</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Move unaligned packed single-precision floating-point values from ymm1 to ymm2/m256 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.0F.W0 11 /r</p>
<p>VMOVUPS zmm2/m512 {k1}{z}, zmm1</p></td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move unaligned packed single-precision floating-point values from zmm1 to zmm2/m512 using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FVM-RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM-MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Note: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p><strong>EVEX.512 encoded version:</strong></p>
<p>Moves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32 memory location, to store the contents of a ZMM register into memory. The destination operand is updated according to the writemask.</p>
<p><strong>VEX.256 and EVEX.256 encoded versions:</strong></p>
<p>Moves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers. Bits (MAX_VL-1:256) of the destination register are zeroed.</p>
<p>128-bit versions:</p>
<p>Moves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.</p>
<p><strong>128-bit Legacy SSE version</strong>: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.</p>
<p>When the source or destination operand is a memory operand, the operand may be unaligned without causing a general-protection exception (#GP) to be generated.</p>
<p><strong>VEX.128 and EVEX.128 encoded versions</strong>: Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p><strong>Operation</strong></p>
<p><strong>VMOVUPS (EVEX encoded versions, register-copy form)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) SRC[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE  DEST[i+31:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVUPS (EVEX encoded versions, store-form)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i](cid:197) SRC[i+31:i]</p>
<p>ELSE *DEST[i+31:i] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p><strong>VMOVUPS (EVEX encoded versions, load-form)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) SRC[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE  DEST[i+31:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVUPS (VEX.256 encoded version, load - and register copy)</strong></p>
<p>DEST[255:0] (cid:197) SRC[255:0]</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p><strong>VMOVUPS (VEX.256 encoded version, store-form)</strong></p>
<p>DEST[255:0] (cid:197) SRC[255:0]</p>
<p><strong>VMOVUPS (VEX.128 encoded version)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>MOVUPS (128-bit load- and register-copy- form Legacy SSE version)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>(V)MOVUPS (128-bit store-form version)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VMOVUPS __m512 _mm512_loadu_ps( void * s);</p>
<p>VMOVUPS __m512 _mm512_mask_loadu_ps(__m512 a, __mmask16 k, void * s);</p>
<p>VMOVUPS __m512 _mm512_maskz_loadu_ps( __mmask16 k, void * s);</p>
<p>VMOVUPS void _mm512_storeu_ps( void * d, __m512 a);</p>
<p>VMOVUPS void _mm512_mask_storeu_ps( void * d, __mmask8 k, __m512 a);</p>
<p>VMOVUPS __m256 _mm256_mask_loadu_ps(__m256 a, __mmask8 k, void * s);</p>
<p>VMOVUPS __m256 _mm256_maskz_loadu_ps( __mmask8 k, void * s);</p>
<p>VMOVUPS void _mm256_mask_storeu_ps( void * d, __mmask8 k, __m256 a);</p>
<p>VMOVUPS __m128 _mm_mask_loadu_ps(__m128 a, __mmask8 k, void * s);</p>
<p>VMOVUPS __m128 _mm_maskz_loadu_ps( __mmask8 k, void * s);</p>
<p>VMOVUPS void _mm_mask_storeu_ps( void * d, __mmask8 k, __m128 a);</p>
<p>MOVUPS __m256 _mm256_loadu_ps ( float * p);</p>
<p>MOVUPS void _mm256 _storeu_ps( float *p, __m256 a);</p>
<p>MOVUPS __m128 _mm_loadu_ps ( float * p);</p>
<p>MOVUPS void _mm_storeu_ps( float *p, __m128 a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<p>Note treatment of #AC varies;</p>
<table>
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E4.nb.</td></tr>
<tr>
<td>If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.</td></tr></table></body></html>